Mechanical stresses within a semiconductor device substrate can be used to modulate device performance. For example, in silicon, hole mobility is enhanced when the silicon film is under compressive stress, while the electron mobility is enhanced when the silicon film is under appropriate tensile stress. Therefore, compressive or tensile stress can be advantageously created in the channel region of a p-MOSFET or an n-MOSFET in order to enhance the performance of such a device.
One conventional approach for creating a desirable stressed silicon channel region is to form such a channel region directly on top of a stress-inducing buffer layer. For example, a tensilely stressed silicon channel layer can be formed by epitaxially growing silicon directly over a thick, relaxed SiGe buffer layer. The lattice constant of germanium is about 4.2% greater than that of silicon, and the lattice constant of a silicon-germanium alloy is linear with respect to its germanium concentration. As a result, the lattice constant of a SiGe alloy with twenty atomic percent of germanium is about 0.8% greater than the lattice constant of silicon. Epitaxial growth of silicon directly on top of such a SiGe buffer layer will yield a silicon channel layer under tensile stress, with the underlying SiGe buffer layer being essentially unstrained, or “relaxed”.
The use of such a strain-inducing SiGe layer has several inherent disadvantages: (1) formation of relaxed SiGe buffer layer relies on defect formation, and consequentially, the SiGe material has a high defect density, which propagates into the silicon channel layer thereabove and poses significant challenges for device applications, such as control of leakage current and device yield, and (2) the presence of the SiGe layer directly underneath the channel region creates processing issues, such as deleterious diffusion of germanium into the strained silicon channel, high resistance silicide formation and altered dopant diffusion.
There is a continuing need for improved semiconductor devices containing high performance MOSFET components.